In conventional semiconductor chips, ICs are formed on the active surfaces of the semiconductor chips with conventional electrical terminals such as bonding pads formed on the active surface. In high-density electrical interconnections, 3D chip stacking was developed with electrical terminals not only disposed on the active surfaces but also on the corresponding back surfaces of the semiconductor chips. Through Silicon Via (TSV) is the enabled technology to vertically stack several chips to assemble 3D chip stacking packages or modules with high powers, high densities, and smaller dimensions. TSV's are electrically-conductive through holes inside a chip penetrating through the top surface and the bottom surface of a chip to create vertical electrical connections without any interposers nor bonding wires. TSV provides directly vertical electrical connections not go through the sidewalls at the edges of the chips to shorten the electrical paths. TSV can further enhance the integration and the performance of an electronic device to greatly reduce the packaging heights and dimensions, to increase the speeds, and to decrease the power consumption of an electronic device. However, each chip will generate heat during operation, therefore, the induced thermal stresses will cause the chip to deform or to warpage and even to break the electrical connections of TSV where stresses are concentrated.
In U.S. Pat. No. 7,091,592 B2 Chen et al. discloses a semiconductor chip with TSV for 3D chip stacking. Each chip has a plurality of through holes with corresponding stud bumps formed by wire bonding inside the through holes. Then the chips are vertically stacked and electrically connected by the stud bumps. However, when the chip experiences thermal stresses causing deformation or warpage, the electrical connections formed by the stud bumps located between the chips are easily broken due to thermal stresses leading to electrical failure.
In U.S. Pat. No. 6,908,785 B2 Kim discloses a semiconductor chip with TSV as shown in FIG. 1. A conventional semiconductor chip 100 primarily comprises a semiconductor substrate 110 and a plurality of conductive metals 120. The semiconductor substrate 110 has a first surface 111, a corresponding second surface 112, and a plurality of through holes 113 penetrating from the first surface 111 to the second surface 112. The conductive metals 120 are disposed inside the through holes 113 and connected with electrical terminals on the first surface 111 and the second surface 112. The through holes 113 with conductive metals 120 disposed inside become TSV. As shown in FIG. 2 again, a plurality of conductive pins 12 are pre-disposed on a plurality of connection pads 11 on the carrier 10 as vertical electrical connections between a plurality of semiconductor chips 100 vertically stacked together. However, in order to electrically connect all the semiconductor chips 100 to the carrier 10, all the conductive pins 12 have to be straight without any bending nor deformation nor shifting and are accurately aligned and inserted into all the corresponding through holes 113. Once one of the conductive pins 12 or the semiconductor chips 100 is bent or deformed or shifted during stacking processes, the conductive pins 12 can not easily insert into the through holes 113 of the semiconductor chips 100 stacked afterwards leading to alignment issues and poor production yields.